Running Quantum Circuits: Quantum Computing in Practice

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circuit depth:
the minimum number of layers of quantum gates executed in parallel required to complete the computation defined by the circuit.
 
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IBM Quantum Processor Types
 
芯片用的是鸟的名字
但是处理器的名字是城市名,并不一定处理器真实所在的城市
 
IBM在其量子计算博客上发表了一篇关于如何更新衡量量子质量和速度的新方法的文章。以下是对文章内容的详尽笔记:

文章标题:

更新我们衡量量子质量和速度的方法

作者与日期:

  • 作者:Andrew Wack 和 David McKay
  • 日期:2023年11月20日

主要内容:

IBM引入了两个新的衡量指标——每层门的错误率(EPLG)和每秒电路层操作数(CLOPSh),以全面反映100+量子比特处理器的性能。

当前量子计算机的基准测试方法:

  • 量子体积(Quantum Volume):虽然量子体积是确保我们不操纵系统理解串扰、错误等的最好方法,但对于大型系统,量子体积只能采样系统的一小部分,并且它只关注设备中最好的几个量子比特,而不是系统整体的平均性能。

量子体积的局限性:

  • 对于足够大的系统,量子体积实验很快将变得太大,以至于我们无法用经典计算机模拟——我们将不知道我们的系统是否能通过量子体积测试。
  • 量子体积设计用于全连接系统,但在2D拓扑结构中,每一步量子体积的提升都会对保真度和门的数量造成压力,因为需要引入许多SWAP门来移动信息。

新的质量和速度指标:

  • 层保真度(Layer Fidelity):提供了一个更细致的理解系统的方法,同时准确捕捉系统运行用户当前运行的电路类型的能力。
  • EPLG(每层门的错误率):通过层保真度的计算,可以近似得到γ̄,即特定设备使用概率错误消除(PEC)协议返回准确错误消除结果的能力。

层保真度的计算方法:

  • 从一组相连的量子比特开始,将它们分割成多个层,每层的量子比特最多只有一个两量子比特门作用于其上。
  • 对每个新层执行随机基准测试,计算每个层的保真度,然后将每层的保真度相乘得到最终的层保真度值。

CLOPS的更新:

  • CLOPSh:更新了CLOPS指标,以更好地反映硬件实际运行电路的方式。CLOPSh定义了“层”的不同含义,只包括可以在系统架构上并行运行的两量子比特门。

CLOPSh的重要性:

  • CLOPSh允许我们以更真实于硬件操作的方式来计算硬件能力,提供了一个更普遍的电路层定义,使得不同处理器之间的性能比较更加公平。

IBM的计划:

  • 到2024年,IBM计划提供一种工具,能够在合理的运行时间内计算具有100个量子比特和100个深度门操作的电路的无偏观测量。

结论:

层保真度和CLOPSh提供了一种新的系统基准测试方法,这对于试图改进和使用IBM硬件的人来说更有意义。这些指标将显示在IBM量子系统资源的100+量子比特设备的系统属性卡上,使系统间的比较、与其他架构的比较以及跨规模的性能提升更加容易。
 
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Transpiler stages

Qiskit's prebuilt transpiler pipeline consists of six fundamental stages:
  1. init - This pass runs any initial passes that are required before the circuit can be embedded into the system. This typically involves unrolling custom instructions and converting the circuit to all single- and two-qubit gates. By default, this validates the circuit instructions and translates multi-qubit gates into single- and two-qubit gates.
  1. layout - This pass applies a layout, mapping the virtual qubits in your circuit to the system's physical qubits.
  1. routing - This pass runs after a layout has been applied and will inject gates (that is, SWAPs) in the original circuit to make it compatible with the system's connectivity (coupling map).
  1. translation - This pass translates the gates in the circuit to the system's basis set of instructions.
  1. optimization - This pass runs an optimization loop to find more efficient decompositions of the quantum circuit until a condition is met (such as a fixed depth).
  1. scheduling - This stage is for any hardware-aware scheduling passes. If the user specifies a scheduling method, this stage accounts for all idle time in the circuit.
If you customize a transpilation workflow, use these stages as a guideline during development.
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6: such as inserting delays into the circuit to account for any idle time on the cubits between the execution of instructions
 
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"PEC: The number of gates grows exponentially fast, so it may not be optimal for a very large circuit."
 
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